Scaling of iDDT Test Methods for Random Logic Circuits

We present a scaling methodology to improve iDDT fault coverage in random logic circuits. The study targets two iDDT test methods: Double Threshold iDDT and Delayed iDDT . The effectiveness of the scaling methodology is assessed through physical test measurements, and studied relative to process variation and impact on circuit performance. The scaling is made possible using a clustering methodology that can significantly improve fault coverage. The results show that without clustering, the effectiveness of the iDDT testing methods considered is greatly reduced as the circuit size increases.